Keywords: geometry effect, ESD modelling, SPICE simulation, whole chip design, nanoelectronics, electrostatic discharge, circuit design
A compact model for electrostatic discharge protection nanoelectronics simulation
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.