Keywords: fin FETs, field–effect transistors, FinFETs, nanoinjection lithography, sub–10 nm fin width, nanotechnology, silicon, etching process, mask–less lithography, photoresist–free lithography, electron beam lithography, plasma CVD, chemical vapour deposition, CMOS technology, continuous scaling
A Si–based bulk FinFET by novel etching process with mask–less and photoresist–free lithography technique
In this study, we used maskless and photoresist–free nano injection lithography (NIL) to develop a sub–10 nm fin width for a Si–based fin field–effect transistor (FinFET) with a 50–nm fin pitch. The active layer was fabricated using double alignment technology (electron–beam lithography and NIL), and the fin trench was filled perfectly by using a high–density plasma chemical vapour deposition process. Advanced plasma and wet etching processes were employed to obtain the fin height. The fabricated FinFET could provide a pathfinding solution for the continuous scaling of complementary metal oxide semiconductor technology.