Keywords: TFET, SOI, MuGFET, MuGTFET, FinFET, voltage reference, multi-gate tunnelling FETs, nanotechnology, simulation, gate stack engineering, doping profile tuning, field effect transistors, nanoelectronics
Complementary multi-gate tunnelling FETs: fabrication, optimisation and application aspects
In this paper fabrication, optimisation and application aspects of complementary Multiple-Gate Tunnelling FETs (MuGTFETs) are presented. Tunnelling FETs (TFETs) are realised in a state-of-the-art low-power multi-gate CMOS technology. n- and p-type tunnelling currents are observed within a single device structure. Digital and analogue device performance is analysed. Measured devices show on-currents in the tens of nA regime, limited by not optimised doping profiles. However, very low leakage currents and promising analogue characteristics are observed. Devices with a channel length of only 65 nm feature an intrinsic gain of more than 300. The scaling potential of multi-gate tunnelling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. Extensive device simulations are carried out, indicating that device behaviour can be optimised by gate stack engineering and tuning of the doping profiles. The devices show low temperature dependence and competitive matching behaviour. Based on the well defined temperature behaviour a new voltage reference circuit is proposed as potential application for the MuGTFET.