Inderscience Publishers

Designing AES cryptographic unit for automatic implementation in low-cost FPGA devices

This paper presents original research results that show viable options for implementation of the advanced encryption standard (AES) cipher (both encoding and decoding paths) in low cost field programmable gate arrays (FPGA). The discussion begins with those aspects of the four basic cipher transformations that are essential for realisation with resources available in FPGA devices, then moves to various possible organisations of the cipher unit and concludes with efficiency and size comparison of results obtained after implementation of the AES-128 version of the method in Spartan-3 devices from Xilinx. The compared design options were implemented with a standard and widely used ISE software with XST synthesis tool. No hand optimisation or fine-tuning of the implementation steps were performed: the synthesis, mapping, placement and routing were all done fully automatically by the software. While this approach will always be inferior to the top-performance hand-optimised designs known in the literature, its automatic implementation brings specific advantages in projects where the unit must co-exist with other parts of the system and elaborated optimisations are either limited or undesired.

Keywords: AES cipher, cryptographic processors, FPGA devices, cryptography, advanced encryption standard, security, field programmable gate arrays, critical computing

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