Keywords: silicon nanowires, germanium nanowires, nanotechnology, vertical nanowires, transistor applications, MOSFETs, 1D nanostructures, field effect transistors, FETs, top–down etching, insulating layers, contact electrodes, isolation process
Fabrication of Si and Ge vertical nanowire for transistor applications
One–dimensional nanostructures, such as nanowhisker, nanorod, nanowire, nanopillar, nanocone, nanotip, nanoneedle, have attracted significant attentions in the past decades owing to their numerous applications in electronics, photonics, energy conversion and storage, and interfacing with biomolecules and living cells. Such one–dimensional nanostructures are potential alternatives to planar metal–oxide–semiconductor field–effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one–dimensional quantum confinement effects. Yet whether nanowire field effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear . Three–dimensional integration and the combination of different material systems are central themes of electronics research. The manufacturing of nanostructured devices relies on either bottom–up approaches such as synthesis or growth process or top–down approaches such as lithography or etching process. Here, vertical Si nanowire and hetero–structure integration of Ge nanowire will be firstly fabricated for the first time to demonstrate the top–down etching process, which is applicable to fabricate vertical transistors. The key step in fabricating 3D vertical devices is the construction of the insulating layer between the contact electrodes. An isolation process without chemical or mechanical polishing steps was also developed to control layer engineering at this length scale.