Inderscience Publishers

Study on nanoparticles embedded multilayer gate dielectric MOS non–volatile memory devices

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Here, we present a computational study on stacked multilayer nanoparticles embedded gate dielectric MOS non–volatile memory devices. Two device structures, one with a pure SiO2 tunnel oxide and other with a stacked HfO2–SiO2 tunnel oxide were compared. The Au nanocrystals were assumed embedded in a Si3N4 layer. The electrical parameters of the composite multilayer were evaluated using Maxwell–Garnett theory and virtual crystal approximation. From the WKB approximation, the direct and the Fowler–Nordheim tunnelling currents were evaluated, and subsequently the I–V characteristics and the flatband voltage shifts were also simulated. The flatband shift simulations were compared with recent experimental results.

Keywords: MOS, multilayer gate, nanoparticles, Fowler–Nordheim tunnelling, nanotechnology, non–volatile memory devices, nanocrystals, electrical parameters, I–V characteristics, flatband voltage shifts, simulation

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