Radiation-hardened electronics product Brochure

ELECTRONIC SYSTEMS2013–2014 SHORT–FORM PRODUCT GUIDERADIATION-HARDENED ELECTRONICS2013-2104 Short-form product guide 1BAE SystemsFront cover photo courtesy of Northrop GrummanOVERVIEWBAE Systems is a global defense, security, and aerospace company, delivering a full range of products and services for air, land, and naval forces, as well as advanced electronics, information technology solutions, and customer support services.The company develops and produces a wide array of radiation hardened space products, from standard components and single-board computers, to complete system payloads. BAE Systems specializes in a broad domain of radiation-hardened electronics, including application-specific integrated circuits (ASICs), microprocessors, memories, FPGAs, and single-board computers. With more than 600 computers in space, including the 16-bit GVSC1750, 32-bit RAD6000®, and the RAD750® family of products, BAE Systems space computers have logged over 5,700 years in orbit.The BAE Systems Semiconductor Technology Center (STC) in Manassas, Virginia, has been providing products and system-level solutions to the commercial, military, and space communities since the early 1980s. A leading manufacturer of radiation-hardened, space-qualified semiconductor devices, the STC offers a complete design, fabrication, packaging, and test facility for very-large-scale integration, or VLSI, wafer and module development and production. The facility features the capabilities to handle procurement of materials through fully screened and qualified mil-spec packaged components.WAFER FABRICATIONBAE Systems leverages both an in-house wafer fabrication facility and external foundry partners to produce advanced semiconductor microcircuits from the 800nm to the 45nm technology nodes.PACKAGINGBAE Systems offers a wide range of wirebond and flip chip hermetic packages to support space, military, avionics, and commercial ASICs and memories. These include families of ceramic quad flat packs, ceramic column grid arrays, plastic ball grid arrays with glob-top, stacked and unstacked die-in multichip modules.TESTINGThe STC test facility encompasses five logic test systems and four memory test systems. It performs production testing and engineering evaluation on wafers and packaged devices over the full military temperature range. The facility has fully equipped VLSI characterization, failure analysis, and reliability laboratories that perform routine and diagnostic testing and evaluation. Failure analysis instruments include photo-emission and scanning electron microscopes and a focused-ion-beam system that supports process diagnostics and semiconductor repair.On site for total-dose testing are J.L. Shepherd Cobalt-60 Gamma source models 109 and 494R, which can be configured for MIL-STD and low-dose rate testing, and an ARACOR 4100 X-ray irradiator. BAE Systems also has access to, and extensive experience with, linear accelerator, flash X-ray, heavy-ion, proton, and neutron test facilities.QUALITYThe Manassas STC and foundry partner fabrication facilities are included in the Defense Logistics Agency (DLA)/Defense Supply Center Columbus (DSCC) Qualified Manufacturer List (QML) for production of avionics and radiation-hardened space parts. The wafer and assembly fabrication is under statistical process control and uses in-line physical and electrical data to assure product quality and reliability in real time, rather than waiting for screening and qualification at the end of the line.Qualification under the DOD’s QML program involves a rigorous validation process by a panel of government agencies and customers. Such qualification means the manufacturer understands user requirements and technical processes to produce — and constantly improve — high-quality, reliable integrated circuits and modules. QML V-level devices with technology conformance inspection are qualified replacements for Qualified Parts List Class S devices. BAE Systems’ space product portfolio is certified and qualified to DLA/DSCC performance specifications MIL-PRF-38535 and MIL-STD-883, including support for legacy requirements.The facility is accredited as a DOD Category 1A Trusted Integrated Circuit Supplier, covering design, foundry, test, packaging, and assembly services. The accreditation expresses the Defense Department’s confidence in BAE Systems’ ability to deliver trusted foundry microelectronics equipment and services to U.S. government end users.TECHNOLOGY CENTER FOR HIGH RELIABILITYTABLE OF CONTENTSSEMICONDUCTOR TECHNOLOGY CENTER 1STANDARD COMPONENTSMEMORY 4MICROPROCESSORS 6FPGAs 6INTERFACE COMPONENTS 8SINGLE-BOARD COMPUTER PRODUCTSRAD750® SINGLE-BOARD COMPUTERS 12RAD750 6U EXTENDED FLEXIBLE ARCHITECTURE 14INTERFACE, MICROCONTROLLER, AND EVALUATION BOARDS 14SOFTWARE TOOLS 15ASIC TECHNOLOGIESASIC TECHNOLOGY 18ASIC DESIGN KIT 20ASIC DESIGN FLOW 20ASIC ENTRY POINTS/TECHNOLOGY ACCESS 21ASIC DESIGN TOOLS 21IP CORES 22SERVICESSERVICES 26QUALITY AND PERFORMANCE EXCELLENCE 262 BAE Systems 2013-2104 Short-form product guide 3STANDARD COMPONENTSRELIABLE, RADIATION HARDENED, SPACE QUALIFIED, HERMETICALLY SEALED, MIL-SCREENED...4 BAE Systems 2013-2104 Short-form product guide 5Memory Part number (PN) Description Configuration Voltage (V) Typical Access/clock (ns)Total-dose (rad[Si])SRAM 251A172 MILLENNIUM 512K x 32 2.5/3.3 12 >100KSRAM 251A137 MILLENNIUM 512K x 40 2.5/3.3 12 >100K SRAM 8394325 MAGNUM 512K x 8 3.3 18 >500KSRAM 8427352 INDEPENDENCE 512K x 32 or 2M x 8 1.5/3.3 13 >1MSRAM 8464575 TITAN 2M x 32 1.2/1.8/2.5 13 >100KSRAM 8485896 TITAN-STACK 8M x 40 1.2/1.8/2.5 ~15 >100KSSRAM 8401349 L2 Cache 128K x 72 1.8/3.3 Read: 4.5 Clock cycle: 7.6>1MPROM 238A790 32K x 8 3.3 TTL 60 >500KPROM 197A807 32K x 8 5.0 CMOS/TTL 27 >200KC-RAM 8406746 256K x 8 3.3 Read: 70 Write: 1000>500KC-RAM 8406746 512K x 8 3.3 Read: 70 Write: 1000>500KC-RAM 8466169 512K x 40 3.3 Read: 70 Write: 1000>500KFIFO 8407971 1K x 36 3.3 Read: 13 Write: 13>1MSingle-event upset (upsets/bit-day) 90% geoLatchup-immune Package Qualified SMD No. <1E-10 Yes 84-lead FP Internally qualifiedN/A<1E-10 Yes 84-lead FP Internally qualifiedN/A<1E-10 Yes 40-lead FP V 5962G07210<1E-12 Yes 86-lead FP Internally qualified Pending<1E-11 Yes 86-lead FP Pending Pending<1E-11 Yes 120-lead FP Pending Pending<1E-10 Yes 340-pin CCGA Internally qualified Pendingimmune Yes 28-lead FP V 5962G02502immune Yes 28-lead FP V 5962R96891<1E-11 Yes 40-lead FP Q 5962H08240<1E-11 Yes 40-lead FP Q 5962H08241<1E-11 Yes 100-lead FP Pending Pending<1E-9 Yes 132-lead CQFP V 5962G08208MEMORY6 BAE Systems 2013-2104 Short-form product guide 7MICROPROCESSORSFPGASMicroprocessors P/N Speed Voltage (V) Total-dose (rad[Si])RAD750 251A161 132 MHz 2.5/3.3 >200KRAD750 8447257 200 MHz 1.8/3.3 >1MFPGAs P/N Voltage (V) Logic cells Total-dose (rad[Si])Single-event upset Effective LET 90% geo (C-latch)RH1020B 197A805 5 2000 >150K 13RH1280B 197A806 5 8000 >100K 17Single-event upset (errors/bit-day (90% W. C. geo)Latchup- immunePackage (CCGA)Qualified SMD No. <1.6 E-10 Yes 360-pin Q 5962R08229<1.6 E-10 Yes 360-pin Q; V-pending 5962H12229Single-event upset Effective LET 90% geo (S-latch)Latchup- ImmunePackage (CQFP)Qualified SMD No.18.8 Yes 84-lead V 5962R909654 Yes 172-lead Q; V-pending 5962R921568 BAE Systems 2013-2104 Short-form product guide 9INTERFACE COMPONENTSInterface componentsP/N Voltage (V) Total-dose (rad[Si])Single-event upset (upsets/bit-day)InterfacesEnhanced PowerPCI8395188 2.5/3.3 200K <1E-10 PCI 2.2, UART, IEEE 1149.1, memory (PROM, EEPROM, SRAM, SDRAM), RAD750/PowerPC, programmable discretesGolden Gate 8451457 1.5/3.3 1M <1E-9 Dual PCI 2.2 32 & 64 bit, UART, IEEE 1149.1, memory (PROM, EEPROM, C-RAM, SRAM, SSRAM, SDRAM), RAD750/PowerPC, SpaceWire (4-ports with router, RMAP), 1553, programmable discretes, external FIFOSpaceWire 8396844 2.5/3.3 200K < 1E-9 Dual PCI 2.2, UART, IEEE 1149.1, memory (PROM, EEPROM, SRAM, SDRAM), SpaceWire (4-ports with router), programmable discretesSpaceWire Endpoint8455613 1.5/3.3 1M <1E-9 UART, IEEE 1149.1, memory (PROM, EEPROM, C-RAM, SRAM), SpaceWire (1 redundant port with RMAP), programmable discretes, SPI, dual I2C, external FIFO, selectMapPCI Peripheral Interface8455611 2.5/3.3 200K <1E-9 PCI 2.2, UART, IEEE 1149.1, memory (PROM, EEPROM, SRAM, SDRAM), programmable discretes, 1553, external FIFOData rates Embedded microcontroller (MIPs)Embedded memoryLatchup- immunePackage Qualified SMD No.PCI peak bandwidth (32bit, 33MHz): 132MB/s write, 126MB/s read4 128Kb Yes 624 CCGA Q 5962R08A04PCI peak bandwidth (64bit, 66MHz): 264MB/s write, 252MB/s read SpaceWire bandwidth: 256Mb/s at 320MHz20 1.2Mb Yes 1144 CCGA Pending PendingPCI peak bandwidth (32bit, 33MHz): 132MB/s write, 126MB/s read SpaceWire bandwidth: 195Mb/s at 260MHz6 256Kb Yes 624 CCGA Q 5962R08A0301SpaceWire bandwidth: 240Mb/s at 320MHz16 256Kb Yes 360 CCGA Pending PendingPCI peak bandwidth (32bit, 33MHz): 132MB/s write, 126MB/s read13 384Kb Yes 624 CCGA Q Pending10 BAE Systems 2013-2104 Short-form product guide 11SINGLE-BOARD COMPUTER PRODUCTSOVER 600 BAE SYSTEMS PROCESSORS ON OVER 200 SATELLITES WITH OVER 5,700 YEARS OF SPACE OPERATION…FLExIBLE ARCHITECTURE AND WIDE RANGE OF PROCESSING OPTIONS...12 BAE Systems 2013-2104 Short-form product guide 13RAD750® SINGLE-BOARD COMPUTERSBoards are not to scaleProduct name (PN) Card format RAD750 (MHz) L2Cache SRAM SDRAM EEPROM SuROM Connector On-card POR Power Ctrl EEPROM SpaceWire 1553Flight EDU Prototype8429311-1 N/A 8413926-1 3U 116 132-ProtoNo None 128MB None 256KB EEPROM Hypertronics No N/A No No251A221-1 N/A 251A219-1 3U 116 132-ProtoNo None 128MB None 256KB EEPROM CompactPCI No N/A No No8403110-1 N/A 8403109-1 3U 132 No None 128MB None 256KB EEPROM Hypertronics No N/A No No8394506-1 8393726-1 8393726-1 6U-160 116 No 8MB None 4MB 64KB PROM (256KB EEPROM-EDU/PROTO)Hypertronics No No No No8394507-1 8394508-1 8393727-1 6U-160 116 No 44MB None 4MB 64KB PROM (256KB EEPROM-EDU/PROTO)Hypertronics No No No No8404785-1 8404784-1 6U-220 132 No 16MB None 4MB 256KB PROM (1MB EEPROM- EDU)Hypertronics Yes No (always On)No No8404760-2 8404755-2 8404750-1 6U-220 132 No 36MB None 4MB 64KB PROM (256KB EEPROM-EDU)Hypertronics No Yes 4-port w/router +8 MB SRAM264 MHzRedundant8427270-1 N/A 8434960-1 6U-160 132 No 12MB None 4MB 64KB PROM Airborn 300-pin Yes Yes No No8403168-1 8389787-1 6U-160 116 No 16MB None 4MB 64KB PROM (256KB EEPROM-EDU)CompactPCI No No No No8419528-1 N/A (Single voltage regulator)8418055-1 6U-160 132 No 20MB None 4MB 64KB PROM Hypertronics Yes Yes No No8403110-1 N/A (Double voltage regulator)8403109-1 6U-160 132 No 20MB None 4MB 64KB PROM Hypertronics Yes Yes No No8477546-1 N/A 8458532-1 6U-160 200 1MB None 128MB None 256KB EEPROM Hypertronics No No No No8477712-1 N/A 8477714-1 6U-160 200 1MB 128MB None None 256KB EEPROM Hypertronics No No 4-port w/router and RMAP+4MB SRAM 320MHzRedundantNotes:– All boards can be customized. For more information, please call the Manassas product line at 866 530 8104.– 6U boards can be easily tailored to have any of the following features: – SRAM: 4MB to 256MB – SDRAM: 128MB to 1GB – NV C-RAM: 4MB to 16MB – SUROM: 256KB EEPROM or 64KB PROM – L2Cache: 1MB – FPGA: Actel RTAX with 1553, SpaceWire or Unique I/O and/or Flash NV Memory – All boards contain an Embedded Microcontroller (EMC) within their respective Bridge ASICs.– Prototype assemblies can be manufactured to IPC J-STD-001E.RAD750 3U cPCI RAD750 6U cPCI RAD750 6U cPCI with Spacewire and 1553 200MHz RAD750 6U cPCI with L2Cache14 BAE Systems 2013-2104 Short-form product guide 15SOFTWARE TOOLSWind River Simics provides a virtualized instance of the RAD750, designed specifically to support software development efforts. This full system simulator includes the RAD750 microprocessor and as the devices found on the RAD750 3U, 6U, and 6U extended boards. The simulator reduces risks and allows software development long before physical hardware is even available. This helps ensure that projects are finished on time and within budget.Wind River Simics is a registered trademark of Wind River.RAD750 6U ExTENDED FLExIBLE ARCHITECTUREINTERFACE, MICROCONTROLLER, AND EVALUATION BOARDSProduct name Part number Card format EMC (MIPs)L2Cache SRAM SDRAM EEPROM SuROM Connector On-card POR Power Ctrl EEPROMSpaceWire 1553SpaceWire 4-port router Evaluation board 8421831-1 6U 6 No 8MB None None 256KB EEPROM CompactPCI No No 4-port w/router NoSpaceWire Endpoint Evaluation board 8458532-1 6U 16 No 4MB None None 256KB CompactPCI No NoRedundant 1-port with RMAP NoMicrocontroller-1553 Interface Board 8451575- E83E4T1111R 3U 13 No 4MB None None64KB PROM or 256KB EEPROM Hypertronics No No No RedundantMicrocontroller-SpaceWire Interface Board8451580- E8354E8R 3U 4 No 8MB None None64KB PROM or 256KB EEPROM Hypertronics No No 4-port w/router NoMicrocontroller-1553- SpaceWire Interface board 8477711-1 3U 20 No 4MB None None64KB PROM or 256KB EEPROM Hypertronics No No4-port w/router and RMAP Redundant Spacewire evaluation boardMemory controlMemory dataMemorybusaddressdataP60X BuscontrolClocks,controls,& JTAGClockMemory addressSpWclockPCI busUARTportOSCOSC– PowerPC 750 ISA– 6 execution units– 32 KB I & D caches– 1 MB L2 cache interface– 260 MIPS at 132 MHz– 400 MIPS at 200 MHz– 1 MB organized 128K x 72– Byte party– PCI 2.2 bus interface– PCI arbitration/central resource– Memory data/address interface– PROM, SRAM, SDRAM, EEPROM, and C-RAM control– EDAC (SEC/DED & SNC/DND)– Auto memory scrubbing– 16550 compatible UART– RAD750 clock control– Timers, interrupts and discretes– JTAG controller (master/slave)– DMA controller– Embedded mirco-controllerJTAGportMemory dataExternal poweron resetCh. ACh. B– 128K × 8 EEPROM or 32K × 8 PROM devices– EDAC – SECDED– 256 KB EEPROM/64 KB PROM– 512K × 8 MCM using 128K × 8 die– EDAC – SECDED– 4MB to 8MB organized 512K × 72– EEPROM Power Switching (externally controlled)– 512K x 40, 2M x 40, or 8M x 40 MCM– EDAC – SECDED– up to 48 MB organized as 512K x 80 per row– up to 144 MB organized as 2M x 80 per row– up to 512 MB organized as 8M x 80 per row– 16M x 32 MCM; 128M x 32 MCM– EDAC – Single nibble correct, double nibble detect– up to 256 MB organized as 16M x 80 per row– up to 1 GB organized as 128M x 80 per row– BC/BM/RT– 64 KB SRAMMemory controlMemory addressSpW 0JTAGport– PCI 2.2 bus interface– Memory data/address interface– SRAM/DRAM control– EDAC-bit nibble– Auto memory scrubbing– Timers, interrupts and discretes– JTAG controller (master/slave)– DMA controller– Embedded microcontrollerSpWclockSpW 1 SpW 2 SpW 3– relocates RAD750 SRAM for SpaceWire usage or– adds RAD750 SDRAMRAD750 CPU L2 CacheEnhanced Power PCI bridgeSuROMCPU EEPROMCPU SRAMCPU SDRAMDual 1553SpaceWireSpaceWire Memory16 BAE Systems 2013-2104 Short-form product guide 17ASIC TECHNOLOGIESHIGH DENSITY, OPTIMIzED POWER AND PERFORMANCE…FLExIBLE ENGAGEMENT MODELS, STATE OF THE ART DEEP SUB-MICRON DESIGN FLOW...DESIGN FINAL PRODUCT18 BAE Systems 2013-2104 Short-form product guide 19ASIC TECHNOLOGYTechnology parameters R25 RH25 RH15 RH45Technology Bulk CMOS Bulk CMOS Bulk CMOS SOIProcess node (nm) 250 250 150 45Voltages (V) 2.5/3.3 3.3 1.5/1.8/2.5/3.3 1.0/1.5/1.8/2.5Wireable gates (millions) up to 6 up to 1 up to 15 up to 300Maximum core frequency 100MHz 90MHz 200MHz 400MHzHigh-speed logic island max frequency 500MHz 150MHz 600MHz 2GHzMetal levels 6 3 personalized 7 10Radiation tolerance — total dose 200Krad(Si) 1Mrad(Si) 1Mrad(Si) 1Mrad(Si)ASIC library optionsStandard cell A – L DStructured ASIC – L – –Mixed signal extensions – – – DMemory optionsSingle port A L L DDual port A L L DPower management optionsClock gating (by design or through synthesis) A L L DMulti-vt design libraries – – L DLow-voltage library extensions A – L DPackage options R25 RH25 RH15 RH45CMOS/LVCMOS A L L DCCGA A L L ACQFP A L L ANumber of signal IO supported up to 512 up to 512 up to 840 up to 1100C4 flip chip A L L AWire bond A L L AIO options3.3V, cold sparable, 5V tolerant A L L –PCI A L L –LVDS A – L DSERDES – – up to 3.125Gbpsup to 5.0GbpsSSTL – – – DHSTL – – – DSchmitt trigger – – – DCategory 1A Trusted FoundryA = AvailableP = Planned or in developmentD = In developmentL = Legacy products onlyA = AvailableP = Planned or in developmentD = In developmentL = Legacy products only20 BAE Systems 2013-2104 Short-form product guide 21ASIC ENTRY POINTS/TECHNOLOGY ACCESSASIC DESIGN TOOLSMentorCadenceProli?cTSSIVHDL/verilog simulation, LVS/DRC veri?cation, DFT insertion and test compressionCustom circuit/analog design and layoutAutomated library cell layoutManufacturing test pattern conversionSynopsys ASIC (standard-cell/gate--array) library cell characterizationLogic/physical/test synthesis, physical design, static timing analysis,custom circuit design and layout, formal/LVS/DRC veri?cation, electromigration andvoltage drop analysis, SSO, signal integrity, custom circuit simulation (fast SPICE)Supplier FunctionASIC DESIGN FLOWASIC DESIGN KITRequirements, architectureLibrary development (if required)Design support Physical design Fabrication, assembly, testDetailed logic design Test supportASIC veri?cation PDR prepASIC speci?cationsTest vectorsDesign kitPreliminary NetlistDropsPreliminary NetlistDropsNetlist,PDR Drop,BAE Systems SignoffFinal text vectors physical design supportFinal Netlist, CDR drop, customer signoffCUSTOMERFOUNDRY SERVICES PROCESS FLOWBAE SYSTEMSKickoff ASIC deliveryPDR CDR RTMEntry Options– Requirements/Specification – RTL (Verilog/VHDL) – Netlist (Verilog/VHDL) – Floorplan – GDSII GraphicsDesign Approaches– Full Custom – Semi-Custom – Standard Cell – Structured ASICDesign Migration– Legacy Design Re-hosting – FPGA to ASIC – Technology Transfers – Commercial to SpaceASIC design kit includes:– Synthesis and timing analysis library – Simulation library (VHDL and Verlog) – Technology databook and documentationTypical netlist handoff shown1. IntroductionThis System Engineering Management Plan (SEMP) sets forth the Manassas Lockheed Martin Federal Systems planfor the conduct and management of the fully integrated engineering effort to implement the On-Board Processor(OBP). component of the Satellite Segment for the Lockheed Martin Broadband Communications System.1.1 SEMP OrganizationThe topics for discussion called for by the SOW are addressed as specific sections within the DID outline.Part I, Systems Engineering . Part I, Systems Engineering, addresses MIL-STD-499A Systems Engineeringprocesses as applied to the OBP Program. These processes are specifically tailored to reflect peculiarities of the OBPProgram such as its NDI/COTS nature reducing development and adapting commercial technology to a militaryoperational and support environment.Part II, Technical Program Planning and Control. Part II, Technical Program Planning and Control, describesspecific planning and control activities for the OBP Program including the integratedengineering effort, relating end items to documentation (document tree), cost elements (CWBS), and the authorityand accountability for technical performance.Part III, Engineering Integration. Part III, Engineering Integration, describes the methods of integrating theengineering efforts into the overall program effort. This focuses on several key areas for the OBP, includingreliability, supportability, and producibility.1.2 Program Overview.The OBP Program integrates an On-Board Digital Signal Processor into the Satellite Segment of the LockheedMartin Broadband Communications System. This overview is provided to establish the context of the OBP Programsystems engineering effort. It is not intended as a complete analysis of the system operation need, mission, orstatement of work.1.3 System Overview.The OBP Program will result in a Broadband Communications System Satellite with state of the art capabilities toprovide users with satellite-based data communications anywhere in the world. This capability requires thedevelopment of a ATM digital switching system, Uplink Processors, and Downlink Processors to reside in theBroadband System’s satellites.1.4 SOW Summary.In order to provide immediate, fast communications services for users around the world, the Lockheed MartinCompany plans to develop a Broadband Communications System. The OBP program is predicated upon the use ofCommercial Off-The-Shelf (COTS), Non-Developmental items (NDI) and commercial standards where possible tominimize cost as well as the time required to place these capabilities in orbit. Thus, it is not viewed as an R&Deffort, but rather one where existing hardware and software are modified if necessary and integrated together toprovide the necessary capabilities. Systems selected to meet program requirements will be NDI which are suitablefor use in the P-3C. The system will be a combination of Contractor Furnished Equipment (CFE), directed CFEduties and who they report to]Speci?cation22 BAE Systems 2013-2104 Short-form product guide 23IP CORESIP cores IP core descriptionFurther informationOCB On-chip bus The OCB (on-chip bus) is used to connect various on-chip functional blocks, often referred to as cores. The OCB has the following two implementation versions: a low-performance version referred to as the low- performance OCB for interconnecting cores that do not have a high data bandwidth requirement and for providing isolation of high data bandwidth cores from cores with lesser performance requirements. A high-performance version referred to as the high performance OCB for interconnecting cores that require high-bandwidth data paths.AIC Analog input/output and configurationThe AIC core provides for the transport of data between the OCB and separate analog to digital (A/D), digital to analog (D/A), and internal register and configuration interfaces. The AIC core masters data transfers between the OCB and D/A interface using a transmit DMA engine. Likewise, it masters data transfers between the A/D interface and OCB using a receive DMA engine.AMCC Advanced memory controller coreThe advanced memory controller core (AMCC) is designed to interface to external memory (SDRAM, SSRAM, SRAM, or ROM ). SRAM can refer to non-synchronous devices as well as to non-volatile devices such a NVRAM or C-RAM. ROM can refer to any type of read-only memory device (e.g., ROM, PROM, EEPROM, Flash ROM). BIST Built in self-test The BIST core provides a comprehensive set of design-for-testability features. It contains the circuitry necessary to perform functional, lab, and manufacturing testing of a chip, and may be configured for chips of different sizes and with different testability requirements. Functions provided by the BIST core include clock control, hardware and software reset, logic BIST, array BIST, scan string connection, labscan, mode signal generation, OCD/OCR control signal generation, and manufacturing test modes.CAT Clock and test The CAT core provides the following functions: test core, logic/array BIST support, manufacturing pin self-test support, reset logic, manufacturing test support, oscillator and register control, system clock divide, phase-locked loop (PLL) management, and power management.CCI Command and control interfaceThe CCI is a single master/multi-slave serial interface and serves as the path for disseminating configuration information and retrieving status from all ASICs.COP Common on-chip processor interfaceThe common on-chip processor (COP) core interfaces OCB connection and an external RAD6000 COP bus to provide processor diagnostic and debug capabilities. The COP core internal interface consists of a low-performance OCB slave stub that allows other cores (e.g., JTAG Slave, EMC) to read or write the COP interface.D1553 DDC 1553 supportThe D1553 core provides the necessary support logic to map a DDC ACE-core into an OCB-based, system-on-chip environment. The DDC ACE-core provides a complete MIL-STD-1553 B solution.DDC_1553 DDC enhanced Min-ACEThe enhanced mini-ACE family (enhanced mini-ACE, micro-ACE, mini-ACE mark 3, micro-ACE TE) of MIL-STD-1553 terminals provides complete interfaces between a host processor and a 1553 bus. These terminals integrate dual transceiver, protocol logic, and 4K words or 64K words of RAM. The BC/RT/MT versions with 64K words of RAM include built-in RAM parity checking.DMAC DMA controller The DMA controller core provides a simple descriptor-based DMA engine that can perform data transfers between any two address spaces accessible via its OCB interface. The DMA controller will operate on descriptor control blocks stored in linked-list format off the OCB address space. Beyond setting up the DMA descriptors, no other host CPU support is required.EMC Embedded microcontrollerThe EMC core provides a simple, micro-controlled sequencer that provides flexibility for handling reset-initialization sequences and error-handling functions. The EMC core is a RISC-based micro-controller that provides simple, logical, arithmetic, branch, and vector interrupt capabilities.FIFO First in, first out The EXT_FIFO core provides the capability to map a general FIFO interface (GFI) core transmit and receive ports to an off-chip FIFO interface. It also provides the data width adjustment from the 4-byte GFI interface to a single-byte external interfaceGFI Generic FIFO interfaceThe GFI core provides for the transport of data between the OCB and a generic user interface consisting of separate transmit, receive, and configuration ports. The GFI core masters data transfers between the OCB and transmit port using a transmit DMA engine. It also masters data transfers between the OCB and receive port using a receive DMA engine. Both DMA engines are controlled via a linked-list descriptor chain.IP cores (cont.)IP core descriptionFurther informationI2C I2C I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance among many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.JTAG Joint test action groupThe JTAG slave core provides a test access port (TAP) and associated logic to support a fully compliant IEEE Standard 1149.1a JTAG interface to the OCB. The JTAG slave core consists of four subcores: an OCB master stub subcore, the JTAG OCB/decoder subcore, the JTAG slave/TAP subcore, and the JTAG slave boundary subcore.LIF Local I/O functions The LIF core provides the support logic to map a RAD6000 synthesizable core (RSC) CPU into an OCB-based, system-on-chip environment. The LIF core supports the memory controller core request and configuration interfaces. The LIF core also provides an interface to the RSC I/O bus and memory busMCTL Memory controller coreThe memory controller core (MCTL) is a block of digital logic that interfaces with external memory. (SDRAM, SSRAM, SRAM, or ROM ). SRAM can refer to non-synchronous devices and to non-volatile devices such as NVRAM or C-RAM. ROM can refer to any type of read-only memory device (e.g., ROM, PROM, EEPROM). MDL Manchester data linkThe MDL core consists of a separate transmitter module and a separate receiver module. The transmitter module (a parallel-to-serial converter) and the receiver module (a serial-to-parallel converter) are used to provide serialized, one-way data transfer between two terminals over the RS-422 physical interface.MISC Miscellaneous The miscellaneous core has a set of registers mapped to the slave OCB interface that provide control and status information. It also provides several primary I/O signals along with sideband signals for connection to other cores within the ASIC.P60X 60x bus The 60x bus core is an electronic circuit that transmits and receives data over the 60x bus used by the PowerPC family of processors, a memory controller interface, and an OCB.PCI PCI - 32 and 64 bit, tgt, mstr, init.The PCI core provides a PCI master and target interface and an optional PCI central resource function. The PCI core provides an OCB application interface that is asynchronous to the PCI interface. Internal buffering of data and command queues is provided by the core along with all control necessary to operate the interfaces and buffers. There are 32- and 64-bit versions of this core.RIF SpaceWire router interfaceThe RIF core provides for the transport of data between the OCB and the SpaceWire router core. It accomplishes this with separate transmit DMA engine and a receive DMA engine. Each engine is controlled via a linked-list descriptor chain.SERDES Serializer/deserializerThe SERDES product reduces board complexity by converting a wide data bus and clock into a serial data stream transmitted through a twisted pair. Our product, which supports a series of industry standard protocols, support up to 3.125 Gbps full duplex in 1 to 16 lanes.SRAM Static random-access memoryThe SRAM (static random-access memory) core is designed to store blocks of data addressed and mapped onto the OCB. UART Universal asynchronous receiver/transmitter The UART (universal asynchronous receiver/transmitter) core transmits and receives data through the serial port, allowing for programmability and implementing the requirements of the 16550 UART.PLL Rad-hard, phase-locked loopThe PLL core is used for clock deskewing in ASIC chips. The internal ASIC clocks are phase-aligned to a common external system clock. The PLL features include a fully integrated mixed-mode PLL design, wide lock-In range: 30 – 250 MHz, and programmable 1x-10x output-to-input frequency ratio.24 BAE Systems 2013-2104 Short-form product guide 25SERVICESQUALIFIED, TRUSTED ANDACCREDITED…DESIGN, PACKAGING, ASSEMBLY, TEST AND SCREENING…26 BAE Systems 2013-2104 Short-form product guide 27ABBREVIATIONS AND ACRONYMS ASIC Application-specific integrated circuit ATPG Automatic test pattern generation CCGA Ceramic column grid array CDR Critical design review CGA Column grid array cPCI CompactPCI CQFP Ceramic quad flat pack C-RAM Chalcogenide random access memory DRC Design rule check DSCC Defense Supply Center Columbus EDU Engineering development unit EEPROM Electrically erasable programmable read-only memory En-PPCI Enhance PowerPCI ASIC FIFO First-in first-out memory FP Flatpack FPGA Field-programmable gate-array GVSC1750 Generic VHSIC spaceborne computer - MIL-STD-1750 HSTL High speed tranceiver logic IP core Intellectual property core LVDS Low voltage differential signal LVS Layout versus schematic MIL-STD Military standard N/A Not applicable NV Non volatile OSC Oscillator PCI Peripheral component interface PDR Preliminary design review P/N Part number POR Power-on reset Power Ctrl Power control PROM Programmable read-only memory QML Qualified manufacturer list RMAP Remote Memory Access Protocol RTL Register transfer logic SDRAM Synchronous dynamic random access memory SERDES Serializer/Deserializer Si Silicon SMD Standard microcircuit drawing SPICE Simulation program with integrated circuit emphasis SRAM Static random access memory SSRAM Synchronous static random access memory SSTL Stub series terminated logic SuROM Start-up read-only memory VHDL VHSIC hardware description language VHSIC Very-high-speed integrated circuitServices DescriptionDesign Expertise in ASIC, FPGA, custom and semi-custom designs. Experienced designers in the areas of digital and mixed signal design, comprehensive logical and physical design methodologies, and the art of identifying and realizing efficient implementations tuned for power-performance and execution platform. Familiarity with design integration of unique and emergent technologies such as chalcogenide phase change material and photonics. Flexible engagement models and entry points from specification to GDSII.FPGA to ASIC conversionsEstablished FPGA-to-ASIC conversion method, based on experience from internal and external development programs. Mapping of design and constraints handled in a structured manner, exploiting target ASIC technology features. Multiple FPGA to single ASIC available.Advanced packaging Broad selection of cost-effective, space-qualified technologies for high-density packaging to meet the needs of high-performance applications. Offers DSCC full mil-standard screens. Wide range of qualified flipchip, wirebond and hermetic ceramic packages available. Memory stacking offered for increased density. Qualified-high reliability and high-performance ceramic column grid array (CCGA) packages for military and plastic ball grid array (BGA) for commercial applications are available.Advanced testing Capabilities include logic and memory testing at wafer and module levels, with full mil-spec temperature test capabilities. Services include test program development through full production including static and dynamic burn-in. Extensive chip diagnostic experience and expertise with scan and other DFT techniques, fault isolation, schmoo plotting and parametric analysis. Support during design is available..Failure analysis Expertise in advanced failure analysis techniques. Failure analysis instruments include photo-emission, transmission and scanning electron microscopes and a focused-ion-beam system that supports technology development and semiconductor diagnostics. Destructive physical analysis (DPA), fault localization and characterization, prohibited materials analysis and counterfeit inspection services available.QUALITY AND PERFORMANCE ExCELLENCE– AS9100 Quality Management System – Trusted Foundry/Trusted Source – Category 1A (Design, foundry, package assembly, and test) – QML (V, Q, K, H, or E) – Class V or Q (radiation hardened space qualified) – Class K, H, or E (hybrid multi-chip module compliant) – Technology Conformance Inspections (TCI) and screening per MIL-PRF-38535 and MIL-STD-883SERVICES28 BAE Systems 2013-2104 Short-form product guideNOTESDisclaimer and copyrightThis document gives only a general description of the product(s) and service(s) and, except where expressly provided otherwise, shall not form any part of any contract. From time to time, changes may be made in the products or the conditions of supply. BAE SYSTEMS is a registered trademark of BAE Systems plc.©2013 BAE Systems. All rights reserved.CS-12-A65-01-2013For more informationBAE Systems 9300 Wellington Road Manassas, Virginia 20110-4122 Telephone 866 530 8104 www.baesystems.com/rad750Cleared for open publication on 02/13 SEMICONDUCTOR TECHNOLOGY CENTER STANDARD COMPONENTS memory MICROPROCESSORS FPGAs INTERFACE COMPONENTS SINGLE-BOARD COMPUTER PRODUCTS RAD750® SINGLE-BOARD COMPUTERS RAD750 6U EXTENDED FLEXIBLE ARCHITECTURE INTERFACE, MICROCONTROLLER, and EVALUATION BOARDS SOFTWARE TOOLS ASIC TECHNOLOGIES ASIC TECHNOLOGY ASIC DESIGN KIT ASIC DESIGN FLOW ASIC ENTRY POINTS/TECHNOLOGY ACCESS ASIC DESIGN TOOLS IP CORES SERVICES services Quality and Performance Excellence