Vista - Architecture Validation Software Brochure

Enable hardware and software verification early in the design cycle. System verification challenges have gone beyond the scope of what RTL can address. Abstracting hardware modeling and moving it earlier in the development process enables faster validation and debug of both the hardware and the software components of the system. SystemC and the Transaction Level Modeling (TLM) 2.0 communication standards enable system-wide verification and hardware software integration much earlier in the design cycle.